1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus, and more particularly, to a clock signal generation circuit and a data output circuit of a semiconductor memory apparatus.
2. Related Art
A conventional semiconductor memory apparatus includes a clock signal generation circuit such as a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit. The semiconductor memory apparatus has improved an operational speed thereof by synchronizing output data by means of an internal clock signal generated from the clock signal generation circuit. The DLL circuit is configured to provide a negative delay to an external clock signal input through a clock input buffer, and thus, generate a clock signal having an advance phase for a predetermined time to transmit the clock signal to a data output circuit. Meanwhile, the PLL circuit is configured to discriminate a frequency and a phase of the input clock signal, and regenerate a clock signal corresponding to the frequency and the phase by means of an oscillator to transmit the clock signal to the data output circuit.
The DLL circuit has an advantage in that the DLL circuit has excellent adaptability to PVT (process, voltage, and temperature) in low-frequency operation and high stability to a jitter component. However, the DLL circuit has a disadvantage in that the DLL circuit is not suitable for a high-frequency operation. On the contrary, the PLL circuit is suitable for the high-frequency operation, but the stability of the PLL circuit deteriorates in the low-frequency operation. In recent years, because the semiconductor memory apparatus has gradually operated at higher speeds, the semiconductor memory apparatus has been installed in an environment using a high-frequency clock signal. Therefore, a lot of semiconductor memory apparatuses are designed to have the PLL circuit. Herein, the PLL circuit used for a data output operation has a negative delay circuit to control a phase of an output clock signal. Like this, in a case when the PLL circuit has the negative delay circuit, the PLL circuit has a disadvantage in that the performance thereof deteriorates.
The semiconductor memory apparatus that has only the DLL circuit or only a PLL circuit could only be adapted to a fixed frequency environment. A semiconductor memory apparatus that is adaptable to a wider frequency band by using selectively the DLL circuit or the PLL circuit has been developed in order to improve that, but even in this case, since the PLL circuit must have the negative circuit, excellent performance, which could not be secured. Consequently, the semiconductor memory apparatus had a problem in that the operational stability thereof deteriorates when performing a high-speed data output operation. As a result, the reliability of a data output operation cannot be largely secured.